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1 2009 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. ? january 2009 cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 idt723614 commercial and industrial temperature ranges idt and the idt logo are registered trademarks of integrated device technology, inc. syncbififo is a trademark of integrated d evice technology, inc. dsc-3146/3 features: ? ? ? ? ? free-running clka and clkb can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) ? ? ? ? ? two independent clocked fifos (64 x 36 storage capacity each) buffering data in opposite directions ? ? ? ? ? mailbox bypass register for each fifo ? ? ? ? ? dynamic port b bus sizing of 36 bits (long word), 18 bits (word), and 9 bits (byte) ? ? ? ? ? selection of big- or little-endian format for word and byte bus sizes ? ? ? ? ? three modes of byte-order swapping on port b ? ? ? ? ? programmable almost-full and almost-empty flags ? ? ? ? ? microprocessor interface control logic ? ? ? ? ? efa , ffa , aea , and afa flags synchronized by clka ? ? ? ? ? efb , ffb , aeb , and afb flags synchronized by clkb ? ? ? ? ? passive parity checking on each port ? ? ? ? ? parity generation can be selected for each port ? ? ? ? ? supports clock frequencies up to 67 mhz ? ? ? ? ? fast access times of 10 ns ? ? ? ? ? available in 132-pin plastic quad flat package (pqf) or space- saving 120-pin thin quad flat package (tqfp) ? ? ? ? ? industrial temperature range (?40 c to +85 c) is available ? ? ? ? ? green parts available, see ordering information functional block diagram mail 1 register input register output register clka csa w/ r a ena mba port-a control logic device control rst clkb csb w/ r b enb port-b control logic mbf1 3146 drw01 mail 2 register write pointer read pointer status flag logic parity gen/check a 0 - a 35 36 ram array 64 x 36 parity generation parity gen/check programmable flag offset register status flag logic input register output register ram array 64 x 36 parity generation read pointer pefb pgb efb aeb ffb afb odd/ even ffa afa fs0 fs1 efa aea pga pefa mbf2 write pointer fifo2 fifo1 36 36 be siz0 siz1 sw0 sw1 bus matching & byte swapping b 0 -b 35 byte matching & byte swapping
2 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 description: the idt723614 is a monolithic, high-speed, low-power cmos bidirectional clocked fifo memory. it supports clock frequencies up to 67mhz and has read access times as fast as 10ns. two independent 64 x 36 dual-port sram fifos on board the chip buffer data in opposite directions. each fifo has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. fifo data on port b can be input and output in 36-bit, 18-bit, and 9-bit formats pin configurations with a choice of big- or little-endian configurations. three modes of byte-order swapping are possible with any bus size selection. communication between each port can bypass the fifos via two 36-bit mailbox registers. each mailbox register has a flag to signal when new mail has been stored. parity is checked passively on each port and may be ignored if not desired. parity generation can be selected for data read from each port. two or more devices can be used in parallel to create wider data paths. notes: 1. electrical pin 1 in center of beveled edge. 2. uses yamaichi socket ic51-1324-828. gnd aeb efb b 0 b 1 b 2 gnd b 3 b 4 b 5 b 6 v cc b 7 b 8 b 9 gnd b 10 b 11 v cc b 12 b 13 b 14 gnd b 15 b 16 b 17 b 18 b 19 b 20 gnd b 21 b 22 b 23 gnd aea efa a 0 a 1 a 2 gnd a 3 a 4 a 5 a 6 v cc a 7 a 8 a 9 gnd a 10 a 11 v cc a 12 a 13 a 14 gnd a 15 a 16 a 17 a 18 a 19 a 20 gnd a 21 a 22 a 23 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 3146 drw02 117 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 v cc v cc a 24 a 25 a 26 a 27 gnd a 28 a 29 v cc a 30 a 31 a 32 gnd a 33 a 34 a 35 gnd b 35 b 34 b 33 gnd b 32 b 31 b 30 v cc b 29 b 28 b 27 gnd b 26 b 25 b 24 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 afb afa ffa csa ena clka w/ r a v cc pga fs 0 odd/ even fs 1 pefa mbf2 rst be gnd sw1 sw0 siz1 mbf1 gnd pefb v cc w/ r b clkb enb csb ffb gnd mba siz0 pgb pqfp (pq132-1, order code: pqf) top view
3 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 tqfp (pn120-1, order code: pf) top view pin configurations (continued) this device is a clocked fifo, which means each port employs a synchro- nous interface. all data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. the clocks for each port are independent of one another and can be asynchronous or coincident. the enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface. b 22 b 21 gnd b 20 b 19 b 18 b 17 b 16 b 15 b 14 b 13 b 12 b 11 b 10 gnd b 9 b 8 b 7 v cc b 6 b 5 b 4 b 3 gnd b 2 b 1 b 0 efb aeb afb a 23 a 22 a 21 gnd a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 gnd a 9 a 8 a 7 v cc a 6 a 5 a 4 a 3 gnd a 2 a 1 a 0 efa aea 3146 drw03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 afa ffa csa ena clka w/ r a v cc pga pefa mbf 2 mba fs 1 fs 0 odd/ even rst gnd be sw1 sw0 siz1 siz0 mbf 1 pefb pgb v cc w/ r b clkb enb csb ffb 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 b 23 a 24 a 25 a 26 v cc a 27 a 28 a 29 gnd a 30 a 31 a 34 a 35 b 35 gnd b 34 b 33 b 32 b 30 b 31 gnd b 29 b 28 b 27 v cc b 26 b 25 b 24 a 32 a 33 the full flag ( ffa , ffb ) and almost-full flag ( afa , afb ) of a fifo are two-stage synchronized to the port clock that writes data to its array. the empty flag ( efa , efb ) and almost-empty ( aea , aeb ) flag of a fifo are two stage synchronized to the port clock that reads data from its array. the idt723614 is characterized for operation from 0c to 70c. note: 1. pin 1 identifier in corner.
4 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 symbol name i/o description a0-a35 port a data i/o 36-bit bidirectional data port for side a. aea port a almost-empty o programmable almost-empty flag synchronized to clka. it is low when the number of 36-bit flag (port a) words in fifo2 is less than or equal to the value in the offset register, x. aeb port b almost-empty o programmable almost-empty flag synchronized to clkb. it is low when the number of 36-bit flag (port b) words in fifo1 is less than or equal to the value in the offset register, x. afa port a almost-full o programmable almost-full flag synchronized to clka. it is low when the number of 36-bit empty flag (port a) locations in fifo1 is less than or equal to the value in the offset register, x. afb port b almost-full o programmable almost-full flag synchronized to clkb. it is low when the number of 36-bit empty flag (port b) locations in fifo2 is less than or equal to the value in the offset register, x. b0-b35 port b data i/o 36-bit bidirectional data port for side b. be big-endian select i selects the bytes on port b used during byte or word data transfer. a low on be selects the most most significant bytes on b0-b35 for use, and a high selects the least significant bytes. clka port a clock i clka is a continuous clock that synchronizes all data transfers through port a and can be asynchronous or coincident to clkb. efa , ffa , afa , and aea are synchronized to the low-to-high transition of clka. clkb port b clock i clkb is a continuous clock that synchronizes all data transfers through port b and can be asynchronous or coincident to clka. port b byte swapping and data port sizing operations are also synchronous to the low-to-high transi tion of clkb. efb , ffb , afb , and aeb are synchro- nized to the low-to- high transition of clkb. csa port a chip select i csa must be low to enable a low-to-high transition of clka to read or write data on port a. the a0-a35 outputs are in the high-impedance state when csa is high. csb port b chip select i csb must be low to enable a low-to-high transition of clkb to read or write data on port b. the b0-b35 outputs are in the high-impedance state when csb is high. efa port a empty flag o efa is synchronized to the low-to-high transition of clka. when efa is low, fifo2 is (port a) empty, and reads from its memory are disabled. data can be read from fifo2 to the output register when efa is high. efa is forced low when the device is reset and is set high by the second low-to-high transition of clka after data is loaded into empty fifo2 memory. efb port b empty flag o efb is synchronized to the low-to-high transition of clkb. when efb is low, the fifo1 is (port b) empty, and reads from its memory are disabled. data can be read from fifo1 to the output register when efb is high. efb is forced low when the device is reset and is set high by the second low-to-high transition of clkb after data is loaded into empty fifo1 memory. ena port a enable i ena must be high to enable a low-to-high transition of clka to read or write data on port a. enb port b enable i enb must be high to enable a low-to-high transition of clkb to read or write data on port b. ffa port a full flag o ffa is synchronized to the low-to-high transition of clka. when ffa is low, fifo1 is full, (port a) and writes to its memory are disabled. ffa is forced low when the device is reset and is set high by the second low-to-high transition of clka after reset. ffb port b full flag o ffb is synchronized to the low-to-high transition of clkb. when ffb is low, fifo2 is full, (port b) and writes to its memory are disabled. ffb is forced low when the device is reset and is set high by the second low-to-high transition of clkb after reset. fs1, fs0 flag-offset selects i the low-to-high transition of rst latches the values of fs0 and fs1, which selects one of four preset values for the almost-full flag and almost-empty flag offset. mba port a mailbox i a high level on mba chooses a mailbox register for a port a read or write operation. when the select a0-a35 outputs are active, a high level on mba selects data from the mail2 register for output, and a low level selects fifo2 output register data for output. mbf1 mail1 register flag o mbf1 is set low by a low-to-high transition of clka that writes data to the mail1 register. writes to the mail1 register are inhibited while mbf1 is set low. mbf1 is set high by a low-to- high transition of clkb when a port b read is selected and both siz1 and siz0 are high. mbf1 is set high when the device is reset. mbf2 mail2 register flag o mbf2 is set low by a low-to-high transition of clkb that writes data to the mail2 register. writes to the mail2 register are inhibited while mbf2 is set low. mbf2 is set high by a low-to- high transition of clka when a port a read is selected and mba is high. mbf2 is set high when the device is reset. pin description
5 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 pin description (continued) symbol name i/o description odd/ odd/even parity i odd parity is checked on each port when odd/ even is high, and even parity is checked when even select odd/ even is low. odd/ even also selects the type of parity generated for each port if parity generation is enabled for a read operation. pefa port a parity error o when any byte applied to terminals a0-a35 fails parity, pefa is low. bytes are organized as flag (port a) a0-a8, a9-a17, a18-a26, and a27-a35, with the most significant bit of each byte serving as the parity bit. the type of parity checked is determined by the state of the odd/ even input. the parity trees used to check the a0-a35 inputs are s hared by the mail2 register to generate parity if parity generation is selected by pga. therefore, if a mail2 read parity generation is setup by having w/ r a low, mba high, and pga high, the pefa flag is forced high regardless of the a0-a35 inputs. pefb port b parity error o when any valid byte applied to terminals b0-b35 fails parity, pefb is low. bytes are organized flag (port b) as b0-b8, b9-b17, b18-b26, b27-b35 with the most significant bit of each byte serving as the parity bit. a byte is valid when it is used by the bus size selected for port b. the type of parity checked is determined by the state of the odd/ even input. the parity trees used to check the b0-b35 inputs are shared by the mail 1 register to generate parity if parity generation is selected by pgb. therefore, if a mail1 read with parity generation is setup by having w/ r b low, siz1 and siz0 high, and pgb high, the pefb flag is forced high regardless of the state of the b0-b35 inputs. pga port a parity i parity is generated for data reads from port a when pga is high. the type of parity generated is generation selected by the state of the odd/ even input. bytes are organized as a0-a8, a9-a17, a18-a26, and a27-a35. the generated parity bits are output in the most significant bit of each byte. pgb port b parity i parity is generated for data reads from port b when pgb is high. the type of parity generated is generation selected by the state of the odd/ even input. bytes are organized as b0-b8, b9-b17, b18-b26, and b27-b35. the generated parity bits are output in the most significant bit of each byte. rst reset i to reset the device, four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while rst is low. this sets the afa , afb , mbf1 , and mbf2 flags high and the efa , efb , aea , aeb , ffa , and ffb flags low. the low-to-high transition of rst latches the status of the fs1 and fs0 inputs to select almost-full and almost-empty flag offsets. siz0, siz1 port b bus size i a low-to-high transition of clkb latches the states of siz0, siz1, and be , and the following selects (port b) low-to-high transition of clkb implements the latched states as a port b bus size. port b bus sizes can be long word, word, or byte. a high on both siz0 and siz1 accesses the mailbox registers for a port b 36-bit write or read. sw0, sw1 port b byte swap i at the beginning of each long word transfer, one of four modes of byte-order swapping is selected by select (port b) sw0 and sw1. the four modes are no swap, byte swap, word swap, and byte-word swap. byte- order swapping is possible with any bus-size selection. w/ r a port a write/read i a high selects a write operation and a low selects a read operation on for a low-to-high port a select transition of clka. the a0-a35 outputs are in the high-impedance state when w/ r a is high. w/ r b port b write/read i a high selects a write operation and a low selects a read operation on for a low-to-high port b select b transition of clkb. the b0-b35 outputs are in the high-impedance state when w/ r b is high.
6 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) symbol rating commercial unit v cc supply voltage range ?0.5 to 7 v v i (2) input voltage range ?0.5 to vcc+0.5 v v o (2) output voltage range ?0.5 to vcc+0.5 v i ik input clamp current, (v i < 0 or v i > v cc ) 20 ma i ok output clamp current, (v o < 0 or v o > v cc ) 50 ma i out continuous output current, (v o = 0 to v cc ) 50 ma i cc continuous current through v cc or gnd 500 ma t stg storage temperature range ?65 to 150 c notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress r atings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to a bsolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded provided the input and output current ratings are observed. symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v v ih high level input voltage 2 ? v v il low-level input voltage ? 0.8 v i oh high-level output current ? ?4 ma i ol low-level output current ? 8 ma t a operating free-air temperature 0 70 c recommended operating conditions electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min. typ. (1) max. unit v oh v cc = 4.5v, i oh = ?4 ma 2.4 v v ol v cc = 4.5 v, i ol = 8 ma 0.5 v i i v cc = 5.5 v, v i = v cc or 0 50 a i oz v cc = 5.5 v, v o = v cc or 0 50 a i cc (2) v cc = 5.5 v, i o = 0 ma, v i = v cc or gnd 1 ma c in v i = 0, f = 1 mhz 4 pf c out v o = 0, f = 1 mhz 8 pf notes: 1 . all typical values are at v cc = 5 v, t a = 25 c. 2. for additional icc information, see the following page.
7 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 calculating power dissipation the i cc(f) current for the graph in figure 1 was taken while simultaneously reading and writing the fifo on the idt723614 with clka and c lkb set to f s . all data inputs and data outputs change state during each clock cycle to consume the highest supply current. data outputs wer e disconnected to normalize the graph to a zero-capacitance load. once the capacitive lead per data-output channel is known, the power dissipatio n can be calculated with the equation below. with i cc(f) taken from figure 1, the maximum power dissipation (p t ) of the idt723614 can be calculated by: p t = v cc x i cc(f) + (c l x v oh 2 x f o ) where: c l = output capacitance load f o = switching frequency of an output v oh = output high level voltage when no reads or writes are occurring on the idt723614, the power dissipated by a single clock (clka or clkb) input running at frequency fs is calculated by: p t =v cc x f s x 0.290 ma/mhz 0 10 20 30 40 50 60 70 0 50 100 150 200 250 300 350 400 fs ? clock frequency ? mhz i cc(f) supply current ma v cc = 5.5v 3146 drw04 80 v cc = 5v v cc = 4.5v f data = 1/2 f s t a = 25 c c l = 0 pf figure 1. typical characteristics: supply current vs clock frequency
8 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 dc electrical characteristics over recommended ranges of supply voltage and operating free-air temperature commercial com'l & ind'l (1) idt723614l15 idt723614l20 symbol parameter min. max. min. max. unit f s clock frequency, clka or clkb ? 66.7 ? 50 mhz t clk clock cycle time, clka or clkb 15 ? 20 ? ns t clkh pulse duration, clka and clkb high 6 ? 8 ? ns t clkl pulse duration, clka and clkb low 6 ? 8 ? ns t ds setup time, a0-a35 before clka and b0-b35 before clkb 4?5?ns t ens setup time, csa , w/ r a, ena and mba before clka ; csb , w/ r b and enb 5 ? 5 ? ns before clkb t szs setup time, siz0, siz1, and be before clkb 4?5?ns t sws setup time, sw0 and sw1 before clkb 5?7?ns t pgs setup time, odd/ even and pga before clka ; odd/ even and pgb before 4 ? 5 ? ns clkb (2) t rsts setup time, rst low before clka or clkb (3) 5?6?ns t fss setup time, fs0 and fs1 before rst high 5 ? 6 ? ns t dh hold time, a0-a35 after clka and b0-b35 after clkb 1?1?ns t enh hold time, csa , w/ r a, ena and mba after clka ; csb , w/ r b, and enb 1 ? 1 ? ns after clkb t szh hold time, siz0, siz1, and be after clkb 2?2?ns t swh hold time, sw0 and sw1 after clkb 0?0?ns t pgh hold time, odd/ even and pga after clka ; odd/ even and pgb after 0 ? 0 ? ns clkb (2) t rsth hold time, rst low after clka or clkb (3) 5?6?ns t fsh hold time, fs0 and fs1 after rst high 4 ? 4 ? ns t skew1 (4) skew time, between clka and clkb for efa , efb , ffa , and ffb 8?8?ns t skew2 (4) skew time, between clka and clkb for aea , aeb , afa , and afb 14 ? 16 ? ns notes: 1. industrial temperature range product for 20ns speed grade is available as a standard device. all other speed grades are avail able by special order. 2. only applies for a clock edge that does a fifo read. 3. requirement to count the clock edge as one of at least four needed to reset a fifo. 4. skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship b etween clka cycle and clkb cycle. (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c; industrial; v cc = 5.0v 10%,t a = 40 c to +85 c)
9 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 commercial com'l & ind'l (1) idt723614l15 idt723614l20 symbol parameter min. max. min. max. unit t a access time, clka to a0-a35 and clkb to b0-b35 2 10 2 12 ns t wff propagation delay time, clka to ffa and clkb to ffb 210212ns t ref propagation delay time, clka to efa and clkb to efb 210212ns t pae propagation delay time, clka to aea and clkb to aeb 210212ns t paf propagation delay time, clka to afa and clkb to afb 210212ns t pmf propagation delay time, clka to mbf1 low or mbf2 high and clkb to 1 9 1 12 ns mbf2 low or mbf1 high t pmr propagation delay time, clka to b0-b35 (2) and clkb to a0-a35 (3) 311313ns t ppe (4) propagation delay time, clkb to pefb 211212ns t mdv propagation delay time, mba to a0-a35 valid and siz1, siz0 to b0-b35 valid 1 11 1 11. 5 ns t pdpe propagation delay time, a0-a35 valid to pefa valid; b0-b35 valid to pefb valid 3 10 3 11 ns t pope propagation delay time, odd/ even to pefa and pefb 311312ns t popb (5) propagation delay time, odd/ even to parity bits (a8, a17, a26, a35) and 2 11 2 12 ns (b8, b17, b26, b35) t pepe propagation delay time, csa , ena, w/ r a, mba, or pga to pefa ; csb , enb, 1 11 1 12 ns w/ r b, siz1, siz0, or pgb to pefb t pepb (5) propagation delay time, csa , ena, w/ r a, mba, or pga to parity bits (a8, a17, 3 12 3 13 ns a26, a35); csb , enb, w/rb, siz1, siz0, or pgb to parity bits (b8, b17, b26, b35) t rsf propagation delay time, rst to ( mbf1 , mbf2 ) high 1 15 1 20 ns t en enable time, csa and w/ r a low to a0-a35 active and csb low and w/ r b210212ns high to b0-b35 active t dis disable time, csa or w/ r a high to a0-a35 at high-impedance and csb high or 1 8 1 9 ns w/ r b low to b0-b35 at high-impedance switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 30 p f notes: 1. industrial temperature range product for 20ns speed grade is available as a standard device. all other speed grades are avail able by special order. 2. writing data to the mail1 register when the b0-b35 outputs are active and siz1, siz0 are high. 3. writing data to the mail2 register when the a0-a35 outputs are active and mba is high. 4. only applies when a new port b bus size is implemented by the rising clkb edge. 5. only applies when reading data from a mail register. (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c; industrial; v cc = 5.0v 10%,t a = 40 c to +85 c)
10 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 b, efb is set low when the fourth byte or second word of the last long word is read. the read pointer of a fifo is incremented each time a new word is clocked to the output register. the state machine that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when the fifo sram status is empty, empty+1, or empty+2. a word written to a fifo can be read to the fifo output register in a minimum of three cycles of the empty flag synchronizing clock. therefore, an empty flag is low if a word in memory is the next data to be sent to the fifo output register and two cycles of the port clock that reads data from the fifo have not elapsed since the time the word was written. the empty flag of the fifo is set high by the second low-to-high transition of the synchronizing clock, and the new data word can be read to the fifo output register in the following cycle. a low-to-high transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t skew1 or greater after the write. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figure 14 and 15). full flag ( ffa , ffb ) the full flag of a fifo is synchronized to the port clock that writes data to its array. when the full flag is high, a memory location is free in the sram to receive new data. no memory locations are free when the full flag is low and attempted writes to the fifo are ignored. each time a word is written to a fifo, the write pointer is incremented. the state machine that controls a full flag monitors a write-pointer and read-pointer comparator that indicates when the fifo sram status is full, full-1, or full-2. from the time a word is read from a fifo, the previous memory location is ready to be written in a minimum of three cycles of the full flag synchronizing clock. therefore, a full flag is low if less than two cycles of the full flag synchronizing clock have elapsed since the next memory write location has been read. the second low-to-high transition on the full flag synchronization clock after the read sets the full flag high and the data can be written in the following clock cycle. a low-to-high transition on a full flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t skew1 or greater after the read. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figure 16 and 17). almost-empty flags ( aea , aeb ) the almost-empty flag of a fifo is synchronized to the port clock that reads data from its array. the state machine that controls an almost-empty flag monitors a write-pointer and a read-pointer comparator that indicates when the fifo sram status is almost-empty, almost-empty+1, or almost- empty+2. the almost-empty state is defined by the value of the almost-full and almost-empty offset register (x). this register is loaded with one of four preset values during a device reset (see reset above). an almost- empty flag is low when the fifo contains x or less long words in memory and is high when the fifo contains (x+1) or more long words. two low-to-high transitions of the almost-empty flag synchronizing clock are required after a fifo write for the almost-empty flag to reflect the new level of fill. therefore, the almost-empty flag of a fifo containing (x+1) or more long words remains low if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (x+1) level. an almost-empty flag is set high by the second low-to-high transition of the synchronizing clock after the fifo write that fills memory to the (x+1) level. a low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time signal descriptions reset the idt723614 is reset by taking the reset ( rst ) input low for at least four port a clock (clka) and four port b clock (clkb) low-to-high transitions. the reset input can switch asynchronously to the clocks. a device reset initializes the internal read and write pointers of each fifo and forces the full flags ( ffa , ffb ) low, the empty flags ( efa , efb ) low, the almost-empty flags ( aea , aeb ) low and the almost-full flags ( afa , afb ) high. a reset also forces the mailbox flags ( mbf1 , mbf2 ) high. after a reset, ffa is set high after two low-to-high transitions of clka and ffb is set high after two low-to-high transitions of clkb. the device must be reset after power up before data is written to its memory. a low-to-high transition on the rst input loads the almost-full and almost-empty offset register (x) with the values selected by the flag select (fs0, fs1) inputs. the values that can be loaded into the registers are shown in table 1. fifo write/read operation the state of port a data a0-a35 outputs is controlled by the port a chip select ( csa ) and the port a write/read select (w/ r a). the a0-a35 outputs are in the high-impedance state when either csa or w/ r a is high. the a0- a35 outputs are active when both csa and w/ r a are low. data is loaded into fifo1 from the a0-a35 inputs on a low-to-high transition of clka when csa is low, w/ r a is high, ena is high, mba is low, and ffa is high. data is read from fifo2 to the a0-a35 outputs by a low-to-high transition of clka when csa is low, w/ r a is low, ena is high, mba is low, and efa is high (see table 2). the port b control signals are identical to those of port a. the state of the port b data (b0-b35) outputs is controlled by the port b chip select ( csb ) and the port b write/read select (w/ r b). the b0-b35 outputs are in the high- impedance state when either csb or w/ r b is high. the b0-b35 outputs are active when both csb and w/ r b are low. data is loaded into fifo2 from the b0-b35 inputs on a low-to-high transition of clkb when csb is low, w/ r b is high, enb is high, efb is high, and either siz0 or siz1 is low. data is read from fifo1 to the b0-b35 outputs by a low-to-high transition of clkb when csb is low, w/ r b is low, enb is high, efb is high, and either siz0 or siz1 is low (see table 3). the setup and hold time constraints to the port clocks for the port chip selects (csa, csb) and write/read selects (w/ r a, w/ r b) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. if a port enable is low during a clock cycle, the port chip select and write/read select can change states during the setup and hold time window of the cycle. synchronized fifo flags each fifo is synchronized to its port clock through two flip-flop stages. this is done to improve flag reliability by reducing the probability of metastable events on the output when clka and clkb operate asynchro- nously to one another. efa , aea , ffa , and afa are synchronized to clka. efb , aeb , ffb , and afb are synchronized to clkb. tables 4 and 5 show the relationship of each port flag to fifo1 and fifo2. empty flags ( efa , efb ) the empty flag of a fifo is synchronized to the port clock that reads data from its array. when the empty flag is high, new data can be read to the fifo output register. when the empty flag is low, the fifo is empty and attempted fifo reads are ignored. when reading fifo1 with a byte or word size on port
11 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 t skew2 or greater after the write that fills the fifo to (x+1) long words. otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see figure 18 and 19). almost full flags ( afa , afb ) the almost-full flag of a fifo is synchronized to the port clock that writes data to its array. the state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the fifo sram status is almost full, almost full-1, or almost full-2. the almost-full state is defined by the value of the almost-full and almost-empty offset register (x). this register is loaded with one of four preset values during a device reset (see reset above). an almost-full flag is low when the fifo contains (64-x) or more long words in memory and is high when the fifo contains [64-(x+1)] or less long words. two low-to-high transitions of the almost-full flag synchronizing clock are required after a fifo read for the almost-full flag to reflect the new level of fill. therefore, the almost-full flag of a fifo containing [64-(x+1)] or less words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words in memory to [64-(x+1)]. an almost-full flag is set high by the second low-to-high transition of the synchronizing clock after the fifo read that reduces the number of long words in memory to [64-(x+1)]. a low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time t skew2 or greater after the read that reduces the number of long words in memory to [64-(x+1)]. otherwise, the subsequent synchro- nizing clock cycle can be the first synchronization cycle (see figure 20 and 21). mailbox registers each fifo has a 36-bit bypass register to pass command and control information between port a and port b without putting it in queue. the mailbox-select (mba, mbb) inputs choose between a mail register and a fifo for a port data transfer operation. a low-to-high transition on clka writes a0-a35 data to the mail1 register when a port a write is selected by csa , w/ r a, and ena with mba high. a low-to-high transition on clkb writes b0-b35 data to the mail2 register when a port b write is selected by csb , w/ r b, and enb with both siz1 and siz0 high. writing data to a mail register sets the corresponding flag ( mbf1 or mbf2 ) low. attempted writes to a mail register are ignored while the mail flag is low. when the port a data outputs (a0-a35) are active, the data on the bus comes from the fifo2 output register when mba is low and from the mail2 register when mba is high. when the port b data outputs (b0-b35) are active, the data on the bus comes from the fifo1 output register when either one or both siz1 and siz0 are low and from the mail2 register when both siz1 and siz0 are high. the mail1 register flag ( mbf1 ) is set high csb w/ r b enb siz1, siz0 clkb b0-b35 outputs port functions h x x x x in high-impedance state none l h l x x in high-impedance state none l h h one, both low in high-impedance state fifo2 write l h h both high in high-impedance state mail2 write l l l one, both low x active, fifo1 output register none l l h one, both low active, fifo1 output register fifo1 read l l l both high x active, mail1 register none l l h both high active, mail1 register mail1 read (set mbf1 high) table 3 ? port-b enable function table csa w/ r a ena mba clka a0-a35 outputs port functions hxxxx in high-impedance state none l h l x x in high-impedance state none lhh l in high-impedance state fifo1 write lhhh in high-impedance state mail1 write llllx active, fifo2 output register none llhl active, fifo2 output register fifo2 read l l l h x active, mail2 register none llhh active, mail2 register mail2 read (set mbf2 high) table 2 ? port-a enable function table almost-full and fs1 fs0 rst almost-empty flag offset register (x) hh 16 hl 12 lh 8 ll 4 table 1 ? flag programming
12 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 dynamic bus sizing the port b bus can be configured in a 36-bit long word, 18-bit word, or 9- bit byte format for data read from fifo1 or written to fifo2. word- and byte- size bus selections can utilize the most significant bytes of the bus (big- endian) or least significant bytes of the bus (little-endian). port b bus size can be changed dynamically and synchronous to clkb to communicate with peripherals of various bus widths. the levels applied to the port b bus size select (siz0, siz1) inputs and the big-endian select ( be ) input are stored on each clkb low-to-high transition. the stored port b bus size selection is implemented by the next rising edge on clkb according to figure 2. only 36-bit long-word data is written to or read from the two fifo memories on the idt723614. bus-matching operations are done after data is read from the fifo1 ram and before data is written to the fifo2 ram. port b bus sizing does not apply to mail register operations. bus-matching fifo1 reads data is read from the fifo1 ram in 36-bit long word increments. if a long word bus size is implemented, the entire long word immediately shifts to the fifo1 output register. if byte or word size is implemented on port b, only the first one or two bytes appear on the selected portion of the fifo1 output register, with the rest of the long word stored in auxiliary registers. in this case, subsequent fifo1 reads with the same bus-size implementation output the rest of the long word to the fifo1 output register in the order shown by figure 2. each fifo1 read with a new bus-size implementation automatically unloads data from the fifo1 ram to its output register and auxiliary registers. therefore, implementing a new port b bus size and performing a fifo1 read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread long word data. when reading data from fifo1 in byte or word format, the unused b0- b35 outputs remain inactive but static, with the unused fifo1 output register bits holding the last data value to decrease power consumption. bus-matching fifo2 writes data is written to the fifo2 ram in 36-bit long word increments. fifo2 writes, with a long-word bus size, immediately store each long word in fifo2 ram. data written to fifo2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. the clkb rising edge that writes the fourth byte or the second word of long word to fifo2 also stores the entire long word in fifo2 ram. the bytes are arranged in the manner shown in figure 2. each fifo2 write with a new bus-size implementation resets the state machine that controls the data flow from the auxiliary registers to the fifo2 ram. therefore, implementing a new bus size and performing a fifo2 write before bytes or words stored in the auxiliary registers have been loaded to fifo2 ram results in a loss of data. port-b mail register access in addition to selecting port-b bus sizes for fifo reads and writes, the port b bus size select (siz0, siz1) inputs also access the mail registers. when both siz0 and siz1 are high, the mail1 register is accessed for a port b long word read and the mail2 register is accessed for a port b long word write. the mail register is accessed immediately and any bus-sizing operation that may be underway is unaffected by the mail register access. after the mail register access is complete, the previous fifo access can resume in the next clkb cycle. the logic diagram in figure 3 shows the previous bus-size selection is preserved when the mail registers are accessed from port b. a port b bus size is implemented on each rising clkb edge according to the states of siz0_q, siz1_q, and be _q. byte swapping the byte-order arrangement of data read from fifo1 or data written to fifo2 can be changed synchronous to the rising edge of clkb. byte-order swapping is not available for mail register data. four modes of byte-order swapping (including no swap) can be done with any data port size selection. the order of the bytes are rearranged within the long word, but the bit order within the bytes remains constant. byte arrangement is chosen by the port b swap select (sw0, sw1) inputs on a clkb rising edge that reads a new long word from fifo1 or writes a new long word to fifo2. the byte order chosen on the first byte or first word of a new long word read from fifo1 or written to fifo2 is maintained until the entire long word is transferred, regardless of the sw0 and sw1 states during subsequent writes or reads. figure 4 is an example of the byte-order swapping available for long words. performing a byte swap and bus size simultaneously for a fifo1 read first rearranges the bytes as shown in figure 4, then outputs the bytes as shown in figure 2. simulta- neous bus-sizing and byte-swapping operations for fifo2 writes, first loads the data according to figure 2, then swaps the bytes as shown in figure 4 when the long word is loaded to fifo2 ram. by a rising clkb edge when a port b read is selected by csb , w/ r b, and enb with both siz1 and siz0 high. the mail2 register flag ( mbf2 ) is set high by a low-to-high transition on clka when port a read is selected by csa , w/ r a, and ena and mba is high. the data in the mail register remains intact after it is read and changes only when new data is written to the register. synchronized synchronized number of 36-bit to clkb to clka words in the fifo1 (1) efb aeb afa ffa 0llhh 1 to x h l h h (x+1) to [64-(x+1)] h h h h (64-x) to 63 h h l h 64 h h l l table 4 ? fifo1 flag operation synchronized synchronized number of 36-bit to clka to clkb words in the fifo2 (1) efa aea afb ffb 0llhh 1 to x h l h h (x+1) to [64-(x+1)] h h h h (64-x) to 63 h h l h 64 h h l l table 5 ? fifo2 flag operation note: 1. x is the value in the almost-empty flag and almost-full flag offset register.
13 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 figure 2. dynamic bus sizing b8 ? b0 a a b b c c (a) long word size (b) word size ? big-endian (c) word size ? little-endian (d) byte size ? big-endian write to fifo1/ read from fifo2 read from fifo1/ write to fifo2 1st: read from fifo1/ write to fifo2 2nd: read from fifo1/ write to fifo2 1st: read from fifo1/ write to fifo2 2nd: read from fifo1/ write to fifo2 1st: read from fifo1/ write to fifo2 2nd: read from fifo1/ write to fifo2 3rd: read from fifo1/ write to fifo2 4th: read from fifo1/ write to fifo2 b e siz1 siz0 b e siz1 siz0 b e siz1 siz0 b e siz1 siz0 l l h h l h l h l x l l byte order on port a: 3146 fig 01 b8 ? b0 b8 ? b0 b8 ? b0 b8 ? b0 b8 ? b0 b8 ? b0 b8 ? b0 b8 ? b0 d d ab c d c d ab a b c d a35 ? a27 a26 ? a18 a17 ? a9 a8 ? a0 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 d c b8 ? b0 (d) byte size ? little-endian 1st: read from fifo1/ write to fifo2 2nd: read from fifo1/ write to fifo2 a b 3rd: read from fifo1/ write to fifo2 4th: read from fifo1/ write to fifo2 b e siz1 siz0 h h l b8 ? b0 b8 ? b0 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9 b35 ? b27 b26 ? b18 b17 ? b9
14 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 parity checking the port a inputs (a0-a35) and port b inputs (b0-b35) each have four parity trees to check the parity of incoming (or outgoing) data. a parity failure on one or more bytes of the port a data bus is reported by a low level on the port parity error flag ( pefa ). a parity failure on one or more bytes of the port b data input that are valid for the bus-size implementation is reported by a low level on the port b parity error flag ( pefb ). odd or even parity checking can be selected, and the parity error flags can be ignored if this feature is not desired. parity status is checked on each input bus according to the level of the odd/even parity (odd/ even ) select input. a parity error on one or more valid bytes of a port is reported by a low level on the corresponding port parity error flag ( pefa , pefb ) output. port a bytes are arranged as a0- a8, a9-a17, a18-a26, and a27-a35. port b bytes are arranged as b0-b8, b9-b17, b18-b26, and b27-b35, and its valid bytes are those used in a port b bus-size implementation. when odd/even parity is selected, a port parity error flag ( pefa , pefb ) is low if any byte on the port has an odd/even number of low levels applied to the bits. the four parity trees used to check the a0-a35 inputs are shared by the mail2 register when parity generation is selected for port a reads (pga = high). when a port a read from the mail2 register with parity generation is selected with csa low, ena high, w/ r a low, mba high, and pga high, the port a parity error flag ( pefa ) is held high regardless of the levels applied to the a0-a35 inputs. likewise, the parity trees used to check the b0-b35 inputs are shared by the mail1 register when parity generation is selected for port b reads (pgb = high). when a port b read from the mail1 register with parity generation is selected with csb low, enb high, w/ r b low, both siz0 and siz1 high, and pgb high, the port b parity error flag ( pefb ) is held high regardless of the levels applied to the b0-b35 inputs. parity generation a high level on the port a parity generate select (pga) or port b parity generate select (pgb) enables the idt723614 to generate parity bits for port reads from a fifo or mailbox register. port a bytes are arranged as a0-a8, a9-a17, a18-26, and a27-a35, with the most significant bit of each byte used as the parity bit. port b bytes are arranged as b0-b8, b9-b17, b18-b26, and b27-b35, with the most significant bit of each byte used as the parity bit. a write to a fifo or mail register stores the levels applied to all nine inputs of a byte regardless of the state of the parity generate select (pga, pgb) inputs. when data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the odd/ even select. the generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. parity bits for fifo data are generated after the data is read from sram and before the data is written to the output register. therefore, the port a parity generate select (pga) and odd/even parity select (odd/ even ) have setup and hold time constraints to the port a clock (clka) and the port b parity generate select (pgb) and odd/ even have setup and hold-time constraints to the port b clock (clkb). these timing constraints only apply for a rising clock edge used to read a new long word to the fifo output register. the circuit used to generate parity for the mail1 data is shared by the port b bus (b0-b35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port a bus (a0-a35) to check parity. the shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip select ( csa , csb ) is low, enable (ena, enb) is high, write/ read select (w/ r a, w/ r b) input is low, the mail register is selected (mba is high for port a; both siz0 and siz1 are high for port b), and port parity generate select (pga, pgb) is high. generating parity for mail register data does not change the contents of the register. figure 3. logic diagrams for siz0, siz1, and be be be be be register mux g1 1 1 d q siz0 q siz1 q be q ? siz0 siz1 be clkb 3146 fi g 02 ? ? ? ?
15 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 a a a d a c a b b b c b d b a b c c c b c a c d d d d a d b d c b8 ? b0 (a) no swap (b) byte swap (c) word swap (d) byte-word swap l l sw1 sw0 sw1 sw0 sw1 sw0 sw1 sw0 l l l h h l h h 3146 fi g 03 a8 ? a0 b8 ? b0 a8 ? a0 a8 ? a0 a8 ? a0 b8 ? b0 b8 ? b0 a35 ? a27 a26 ? a18 a17 ? a9 b35 ? b27 b26 ? b18 b17 ? b9 a35 ? a27 a26 ? a18 a17 ? a9 b35 ? b27 b26 ? b18 b17 ? b9 a35 ? a27 a26 ? a18 a17 ? a9 b35 ? b27 b26 ? b18 b17 ? b9 a35 ? a27 a26 ? a18 a17 ? a9 b35 ? b27 b26 ? b18 b17 ? b9 figure 4. byte swapping (long word size example)
16 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 figure 5. device reset loading the x register with the value of eight clka rst ffa ffb efb aea clkb efa fs1,fs0 3146 drw05 t rsts t rsth t fsh t fss t wff 0,1 afa mbf1 , mbf2 t wff aeb afb t wff t ref t wff t ref t rsf t pae t paf t pae t paf
17 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 note: 1. siz0 = high and siz1 = high writes data to the mail2 register clkb enb sw1, sw0 ffb w/ r b b0-b35 be pefb odd/ even high 3146 drw 07 t ens t ens t ens t enh csb siz1, siz0 valid valid t pdpe not (1,1) (1) (0,0) t dh t szh t szh t ens t enh t ppe (0,0) t sws t swh t szs t szs t ds data swap table for long-word writes to fifo2 figure 7. port-b long-word write cycle timing for fifo2 3146 drw06 clka ffa ena a0 - a35 mba csa w/ r a t ens t ens t ens t ens t ds t enh t enh t enh t enh t dh w1 (1) w2 (1) t ens t enh t enh t ens no operation odd/ even pefa valid valid t pdpe t pdpe high t clk t clkh t clkl note: 1. written to fifo1. figure 6. port-a write cycle timing for fifo1 swap mode data written to fifo2 data read from fifo2 sw1 sw0 b35-27 b26-18 b17-b9 b8-b0 a35-27 a26-a18 a17-a9 a8-a0 llabcdabcd lhdcbaabcd hlcdababcd hhbadcabcd
18 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 clkb sw1, sw0 enb ffb w/ r b be high 3146 drw08 pefb odd/ even big- endian b18-b35 little- endian b0-b17 siz1, siz0 csb (0, 1) not (1,1) (1) t enh t enh t enh t swh t szh t szh t szh t szs t szs t szs t szs t ds t ds valid valid t pdpe t dh t dh t szh t sws (0, 1) t ens t ens t ens t ens t ppe notes: 1. siz0 = high and siz1 = high writes data to the mail2 register. 2. pefb indicates parity error for the following bytes: b35-b27 and b26-b18 for big-endian bus, and b17-b9 and b8-b0 for little-endian bus. figure 8. port-b word write cycle timing for fifo2 data swap table for word writes to fifo2 data written to fifo2 mode no. big-endian little-endian sw1 sw0 b35-27 b26-18 b17-b9 b8-b0 a35-27 a26-a18 a17-a9 a8-a0 ll 1 a b c d a b c d 2c d a b lh 1 d c b a a b c d 2b a d c hl 1 c d a b a b c d 2a b c d hh 1 b a d c a b c d 2d c b a data read from fifo2 swap w rite
19 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 ffb csb w/ r b siz1, siz0 clkb 3146 drw09 high sw1, sw0 be odd/even b0- b8 (1,0) (1,0) not (1,1) (1) t ens t enh t sws t szh t szh t szs enb little- endian valid valid valid valid big- endian b27- b35 pefb t ppe t pdpe t pdpe t pdpe t ds t ds t dh t dh t ens t ens t szh t szs t szs t szs t szh t enh t enh t ens t enh (1,0) (1,0) notes: 1. siz0 = high and siz1 = high writes data to the mail2 register. 2. pefb indicates parity error for the following bytes: b35?b27 for big-endian bus and b17?b9 for little-endian bus. data swap table for byte writes to fifo2 figure 9. port-b byte write cycle timing for fifo2 data read from fifo2 swap w rite data written to fifo2 mode no. big-endian little-endian sw1 sw0 b35-27 b8-b0 a35-27 a26-a18 a17-a9 a8-a0 1a d 2b c 3c b 4d a 1d a 2c b 3b c 4a d 1c b 2d a 3a d 4b c 1b c 2a d 3d a 4c b l l l h h l h h a b c d a b c d a b c d a b c d
20 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 notes: 1. siz0 = high and siz1 = high selects the mail1 register for output on b0-b35. 2. data read from fifo1. clkb enb sw1, sw0 efb w/ r b pgb, be odd/ even high 3146 drw10 csb siz1, siz0 not (1,1) (1) t pgh t pgs t szh t szh t enh (0,0) t sws b0-b35 not (1,1) (1) previous data w1 (2) w2 (2) t dis t ens t enh t swh t ens no operation (0,0) t szs t szs t en t a t a data swap table for fifo long-word reads from fifo1 figure 10. port-b long-word read cycle timing for fifo1 data written to fifo1 swap mode data read from fifo1 a35-27 a26-a18 a17-a9 a8-a0 sw1 sw0 b35-27 b26-18 b17-b9 b8-b0 ab c d l l a b c d ab c d l h d c b a ab c d h l c d a b ab c d h h b a d c
21 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 clkb enb sw1, sw0 efb w/ r b pgb, be odd/ even high 3146 drw11 csb siz1, siz0 not (1,1) (1) t pgh t pgs t szh t szh (0,1) t sws b0-b17 not (1,1) (1) previous data t ens t enh t swh no operation previous data b18-b35 little- endian big- endian read 1 read 1 read 2 read 2 (0,1) (2) (2) t szs t szs t en t a t a t a t a t dis t dis notes: 1. siz0 = high and siz1 = high selects the mail1 register for output on b0-b35. 2. unused word b0-b17 or b18-b35 holds last fifo1 output register data for word-size reads. data swap table for word reads from fifo1 figure 11. port-b word read cycle timing for fifo1 data written to fifo1 swap mode read no. big-endian little-endian a35-a27 a26-a18 a17-a9 a8-a0 sw1 sw0 b35-b27 b26-b18 b17-b9 b8-b0 1a b cd abcd l l2cd ab 1d c ba abcd l h2ba dc 1c d ab abcd h l2ab cd 1b a dc abcd h h2d cba data read from fifo1
22 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 notes: 1. siz0 = high and siz1 = high selects the mail1 register for output on b0-b35. 2. unused bytes hold last fifo1 output register data for byte-size reads. efb csb w/ r b siz1, siz0 enb clkb 3146 drw12 high sw1, sw0 be pgb, odd/ even b0-b8 b27-b35 read 4 read 1 read 2 read 4 read 1 read 3 read 3 previous data previous data read 2 (1,0) (1,0) (1,0) not (1,1) (1) no operation t dis t dis t en t pgh t pgs not (1,1) (1) not (1,1) (1) not (1,1) (1) (1,0) t enh t swh t szh t szh t szs t szs t ens t sws t a t a t a t a t a t a t a t a data swap table for byte reads from fifo1 figure 12. port-b byte read cycle timing for fifo1 1a d 2b c abc dll3 c b 4d a 1d a 2c b abc dlh3 b c 4a d 1c b 2d a abc dhl3 a d 4b c 1b c 2a d abc dhh3 d a 4c b data written to fifo 1 swap mode read big- little- no. endian endian a35-a27 a26-a18 a17-a9 a8-a0 sw1 sw0 b35-b27 b8-b0 data read from fifo 1
23 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 3146 drw13 clka efa ena a0 - a35 mba csa w/ r a t enh t enh previous data word 1 word 2 (1) (1) t enh no operation pga, odd/ even high t pgh t pgh t clk t clkh t clkl t ens t a t pgs t a t pgs t ens t ens t dis t en t mdv note: 1. read from fifo2. figure 13. port-a read cycle timing for fifo2 notes: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for efb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of efb high may occur one clkb cycle later than shown. 2. port-b size of long word is selected for fifo1 read by siz1 = low, siz0 = low. if port-b size is word or byte, efb is set low by the last word or byte read from fifo1, respectively. figure 14. efb efb efb efb efb flag timing and first data read when fifo1 is empty csa w r a mba ffa a0 - a35 clkb efb csb w/ r b siz1, siz0 ena enb b0 -b35 clka 12 3146 drw14 t ens t ens t enh t enh t ds t dh t ens t enh w1 fifo1 empty low high low low low w1 high t clk t clkh t clkl t skew1 (1) t clkh t clk t clkl t ref t ref t a
24 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 csb w/ r b siz1, siz0 ffb b0 - b35 clka efa csa w/ r a mba enb ena a0 -a35 clkb 12 3146 drw15 t ens t ens t enh t enh t ds t dh t ens t enh w1 fifo2 empty low high low low low w1 high t clk t clkh t skew1 (1) t clkh t clk t ref t ref t a t clkl t clkl notes: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for efa to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then the transition of efa high may occur one clka cycle later than shown. 2. port b size of long word is selected for fifo2 write by siz1 = low, siz0 = low. if port b size is word or byte t skew1 is referenced to the rising clkb edge that writes the last word or byte of the long word, respectively. figure 15. efa efa efa efa efa flag timing and first data read when fifo2 is empty
25 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 csb efb siz1, siz0 enb b0 - b35 clkb ffa clka csa 3146 drw16 w r a 12 a0 - a35 mba ena t ens t enh t ens t ens t ds t enh t enh t dh to fifo1 previous word in fifo1 output register next word from fifo1 low w/ r b low low high low high fifo1 full t clk t clkh t clkl t a t skew1 (1) t clk t clkh t clkl t wff t wff notes: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ffa to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then ffa may transition high one clka cycle later than shown. 2. port b size of long word is selected for fifo1 read by siz1 = low, siz0 = low. if port b size is word or byte, t skew1 is referenced from the rising clkb edge that reads the last word or byte of the long word, respectively. figure 16. ffa ffa ffa ffa ffa flag timing and first available write when fifo1 is full.
26 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 notes: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for ffb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then ffb may transition high one clkb cycle later than shown. 2. port b size of long word is selected for fifo2 write by siz1 = low, siz0 = low. if port b size is word or byte, ffb is set low by the last word or byte write of the long word, respectively. figure 17. ffb ffb ffb ffb ffb flag timing and first available write when fifo2 is full notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for aeb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then aeb may transition high one clkb cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = high, mba = low), fifo1 read ( csb = low, w/ r b = low, mbb = low). 3. port b size of long word is selected for fifo1 read by siz1 = low, siz0 = low. if port b size is word or byte, aeb is set low by the last word or byte read of the long word, respectively. figure 18. timing for aeb aeb aeb aeb aeb when fifo1 is almost-empty csa efa mba ena a0 - a35 clka ffb clkb csb 3146 drw17 w/ r b 12 b0 - b35 siz1, siz0 enb t ens t enh t ens t ens t ds t enh t enh t dh to fifo2 previous word in fifo2 output register next word from fifo2 low w/ r a low low high low high fifo2 full t clk t clkh t clkl t a t skew1 (1) t clk t clkh t clkl t wff t wff aeb clka enb 3146 drw18 ena clkb 2 1 t ens t enh t ens t enh x long word in fifo1 (x+1) long words in fifo1 t skew2 (1) t pae t pae
27 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 aea clkb ena 3146 drw19 enb clka 2 1 t ens t enh t ens t enh (x+1) long words in fifo2 x long words in fifo2 t skew2(1) t pae t pae notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for aea to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then aea may transition high one clka cycle later than shown. 2. fifo2 write ( csb = low, w/ r b = high, mbb = low), fifo2 read ( csa = low, w/ r a = low, mba = low). 3. port b size of long word is selected for fifo2 write by siz1 = low, siz0 = low. if port b size is word or byte, t skew2 is referenced from the rising clkb edge that writes the last word or byte of the long word, respectively. figure 19. timing for aea aea aea aea aea when fifo2 is almost-empty afa clka enb 3146 drw20 ena clkb 12 t ens t enh t ens t enh [64-(x+1)] long words in fifo1 (64-x) long words in fifo1 t skew2 (1) t paf t paf notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for afa to transition high in the next clka cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then afa may transition high one clkb cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = high, mba = low), fifo1 read ( csb = low, w/ r b = low, mbb = low). 3. port b size of long word is selected for fifo1 read by siz1 = low, siz0 = low. if port b size is word or byte, t skew2 is referenced from the last word or byte read of the long word, respectively. figure 20. timing for afa afa afa afa afa when fifo1 is almost-full afb clkb ena 3146 drw21 enb clka 12 t ens t enh t ens t enh [64-(x+1)] long words in fifo2 (64-x) long words in fifo2 t skew2 (1) t paf t paf notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for afb to transition high in the next clkb cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then afb may transition high one clka cycle later than shown. 2. fifo2 write ( csb = low, w/ r b = high, mbb = low), fifo2 read ( csa = low, w/ r a = low, mba = low). 3. port b size of long word is selected for fifo2 write by siz1 = low, siz0 = low. if port b size is word or byte, afb is set low by the last word or byte read of the long word, respectively. figure 21. timing for afb afb afb afb afb when fifo2 is almost-full
28 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 note: 1. port b parity generation off (pgb = low). figure 22. timing for mail1 register and mbf1 mbf1 mbf1 mbf1 mbf1 flag 3146 drw22 clka ena a0 - a35 mba csa w/ r a clkb mbf1 csb siz1, siz0 enb b0 - b35 w/ r b w1 t ens t enh t dh t en t enh w1 (remains valid in mail1 register after read) fifo1 output register t ds t pmf t pmf t ens t mdv t pmr t dis
29 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 note: 1. port-a parity generation off (pga = low). figure 24. odd/ even even even even even . w/ r r r r r a, mba, and pga to pefa pefa pefa pefa pefa timing figure 23. timing for mail2 register and mbf2 mbf2 mbf2 mbf2 mbf2 flag 3146 drw24 odd/ even pefa pga mba w/ r a valid valid valid valid t pope t pepe t pope t pepe 3146 drw23 clkb enb b0 - b35 siz1, siz0 csb w/ r b clka mbf2 csa mba ena a0 - a35 w/ r a w1 t enh t dh t enh t en fifo2 output register w1 (remains valid in mail2 register after read) t szh t ens t szs t ds t pmf t pmf t ens t pmr t mdv t dis
30 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 january 14, 2009 3146 drw25 odd/ even pefb pgb siz1, siz0 w/ r b valid valid valid valid t pope t pepe t pope t pepe figure 25. odd/ even even even even even . w/ r r r r r b, siz1, siz0, and pgb to pefb pefb pefb pefb pefb timing figure 27. parity generation timing when reading from the mail1 register 3146 drw27 odd/ even b8, b17, b26, b35 pgb siz1, siz0 w/ r b mail1 data generated parity generated parity mail1 data csb low t en t mdv t pepb t popb t pepb figure 26. parity generation timing when reading from the mail2 register 3146 drw26 odd/ even a8, a17, a26, a35 pga mba w/ r a mail2 data generated parity generated parity mail2 data csa low t en t pepb t mdv t popb t pepb note: 1. ena is high. note: 1. enb is high.
31 commercial and industrial temperature ranges idt723614 cmos syncbififo ? ? ? ? ? with bus-matching and byte swapping 64 x 36 x 2 commercial and industrial january 14, 2009 note: 1. includes probe and jig capacitance. figure 28. load circuit and voltage waveforms 3146 drw28 from output under test 30 pf 1.1 k ? 5 v 680 ? load circuit 3 v gnd timing input data, enable input gnd 3 v 1.5 v 1.5 v voltage waveforms setup and hold times voltage waveforms pulse durations voltage waveforms enable and disable times voltage waveforms propagation delay times 3 v gnd gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v output enable low-level output high-level output 3 v v ol gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v v oh ov gnd v oh v ol 1.5 v 1.5 v 1.5 v 1.5 v input in-phase output high-level input low-level input 1.5 v 3 v t plz t phz t pzl t pzh (1) t s t h t w t pd t pd
32 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 fifohelp@idt.com www.idt.com notes: 1. industrial temperature range product for 20ns speed grade is available as a standard device. all other speed grades are avail able by special order. 2. green parts are available. for specific speeds and packages contact your sales office. ordering information 3146 drw29 723614 64 x 36 x 2 syncbififo ? device type x xx x x power speed package clock cycle time (t clk ) speed in nanoseconds process/ temperature range blank i (1) pf pqf 15 20 l commercial (0 c to +70 c) industrial (40 c to +85 c) thin quad flat pack (tqfp, pn120-1) plastic quad flat pack (pqfp, pq132-1) commercial only com'l & ind'l low power x g green xxxxxx datasheet document history 03/05/2002 pgs. 1, 8, 9 and 32. 06/06/2005 pgs. 1, 2, 3 and 32. 01/14/2009 pg. 32.

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